The present invention relates to electrochemical planarization of metal surfaces.
Double layer metallurgy (DLM) is a microelectronic fabricating technique for creating a two-layer structure of metal strips in a circuit. The strips, or "lines," act as wires to connect different components of the circuit. The lower layer of metal is deposited into trenches in a non-conducting substrate. The second, upper layer of lines is deposited on top of the lower one. Lines of the upper and lower layers can cross and interconnect, allowing more flexible inter-component wiring than is possible with only a single layer of metal.
DLM fabrication starts with a flat substrate, which might be a silicon wafer or a slab of alumina, glass, or polymer. The substrate could also be a microelectronic structure of transistors, resistors, and capacitors which has been built up on a base substrate by conventional chip-making or chip-packaging techniques (diffusion, lithography, etching, etc.) and which has been made plane on its top surface.
In general the plane surface of the substrate will receive a patterned layer of polyimide (a polymer plastic material) before the first, lower layer of copper or other conductive metal is plated on. The polyimide layer is about 10 to 150 micron thick. (A micron, .mu.m, or micrometer, is a millionth of a meter. 100 microns is a tenth of a millimeter or 0.004 inch.) The polyimide layer is patterned with gaps through which the bare substrate is exposed. The gaps, because they are generally elongated to form the metal lines, are called trenches.
FIG. 1, labelled "prior art," shows a cross-section of a substrate S with a polyimide P layer. Two trenches are shown. The narrow trench on the left is bordered by two sections of the-polyimide P layer. A left-hand edge of a wide trench is shown on the right.
Copper is damascene plated onto the patterned substrate S and polyimide P, blanketing both with a layer of copper metal. This is shown in FIG. 2, labelled "prior art," where the copper is indicated by "Cu". The copper layer tends toward uniform thickness, but will bridge small openings in the polyimide P pattern, which tend to fill in as the plating accumulates. The POR (Plan of Record) commercial electroplating process exhibits this behavior.
If the trenches are narrow only a crease or cleft R is left in the upper surface of the copper plated layer, as shown in FIG. 2. Narrow polyimide gaps yield trenches with relatively small cleft depth. Since the surface becomes flatter as the copper thickness increases, it is said to be "planarized" by the copper fill-in.
On the other hand, wide trenches in the polyimide remain un-planarized after plating, as is shown on the right in FIG. 2. The copper layer is generally uniform in thickness, so it follows the original surface of the polyimide P layer, except for rounding of sharp corners.
Planarization (planing) of the first metal layer is required for DLM. FIG. 3, labelled "prior art," shows the copper layer of FIG. 2 after planarization.